Senior Physical Design Engineer
- Ho Chi Minh City
- Permanent
- Full-time
- Execute the Netlist-to-GDS design process, which involves floor planning, placement, timing optimization, clock tree synthesis, and routing.
- Provide assistance for STA timing analysis and resolution.
- Conduct physical verification, which involves doing DRC, LVS comparison, analyzing IR drop, and conducting DFM analysis.
- Electrical Engineering/Computer Science.
- At least 3- 5 years of full-time, hands-on experience in relevant role.
- Proficient in using Cadence Innovus or Synopsys ICC2/Fusion Compiler.
- TOEIC score between 730 and 855 is desirable.
- Prior expertise in IC design at 65/40/28nm will be advantageous.